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NXP Semiconductors
PCA85132
LCD driver for low multiplex rates
6.2 Pin description
Table 4.
Pin description
Symbol
SDAACK [1]
SDA [1]
SCL
CLK
V DD
SYNC
OSC
T1, T2, and T3
A0 and A1
SA0
V SS [2]
V LCD
BP2 and BP0
S0 to S79
BP0, BP2, BP1, and BP3
S80 to S159
BP3 and BP1
Pin
1 to 3
4 to 6
7 to 9
10
11 to 13
14
15
16, 17, and 18 to 20
21, 22
23
24 to 26
27 to 29
30, 31
32 to 111
112 to 115
116 to 195
196, 197
Description
I 2 C-bus acknowledge output
I 2 C-bus serial data input
I 2 C-bus serial clock input
clock input and output
supply voltage
cascade synchronization input and output
selection of internal or external clock
dedicated testing pins; to be tied to V SS in
application mode
subaddress inputs
I 2 C-bus slave address input
ground supply voltage
LCD supply voltage
LCD backplane outputs
LCD segment outputs
LCD backplane outputs
LCD segment outputs
LCD backplane outputs
[1]
[2]
For most applications SDA and SDAACK are shorted together (see Section 14.3 on page 44 ).
The substrate (rear side of the die) is connected to V SS and should be electrically isolated.
PCA85132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 July 2013
? NXP B.V. 2013. All rights reserved.
5 of 62
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